1. Technical Field
The present invention relates generally to an integrated circuit, and more particularly to a semiconductor memory apparatus, an operating method thereof, and a data processing system using the same.
2. Related Art
A memory apparatus includes a redundancy cell for replacing a failed main memory cell in order to secure the yield. Furthermore, after the failed main memory cell is replaced with the redundancy cell through a repair operation, the memory apparatus stores the address of the redundancy cell so as to change the address of the repaired main memory cell into that of the redundancy cell. The method for storing a repair address has developed from a method using a fuse to a method using a code addressable memory (CAM).
FIG. 1 is a configuration diagram of a known semiconductor memory apparatus.
Referring to FIG. 1, the known memory apparatus 10 includes a memory area 110, a page buffer circuit 120, an input/output control circuit 130, a peripheral circuit 140, and a controller 150.
The memory area 110 may include a plurality of planes, and each of the planes may include a plurality of banks BANK0 and BANK1. Furthermore, the plane may include redundancy memory areas RED0 and RED1 for replacing a failed main memory cell included in the banks BANK0 and BANK1, when a failure occur in the main memory cell. In general, the redundancy memory cells RED0 and RED1 are provided to correspond to the respective banks BANK0 and BANK1.
The page buffer circuit 120 may include main page buffers PB0 and PB1 and redundancy page buffers RPB0 and RPB1. The main page buffers PB0 and PB1 are configured to transmit and receive data to and from main memory cells inside the banks BANK0 and BANK1, and the redundancy page buffers RPB0 and RPB1 are configured to transmit and receive data to and from redundancy memory cells inside the redundancy memory areas RED0 and RED1.
The input/output control circuit 130 is configured to output data latched in the page buffer circuit 120 to the outside through a global data line GDL or receive data provided from outside through the global data line GDL and provide the received data to the page buffer circuit 120.
The peripheral circuit 140 includes circuits configured to program data into the memory area 110 or read data stored in the memory area 110. For example, the circuits may include an address decoder, a voltage supply circuit and the like.
The controller 150 is configured to control the memory area 110, the page buffer circuit 120, the input/output control circuit 130, and the peripheral circuit 140. In particular, the controller 150 outputs a control signal for selecting a page buffer forming the page buffer circuit 120 according to whether an address provided to access the memory area 110 during a program/read/erase operation is a repair address or not.
Referring to FIG. 1, it can be seen that one bank BANK and one main page buffer PB are coupled to each other through a bit line, and one redundancy memory area RED and one redundancy page buffer RPB are coupled to each other through a bit line. That is, the known semiconductor memory apparatus allocates a redundancy memory area to each bank, and repairs a memory cell of a specific bank into a redundancy memory area formed to correspond to the specific bank, when a failure occurs in the memory cell.
Suppose that a failed cell occurs in the memory bank BANK0 and is repaired and replaced with the corresponding redundancy memory area RED0. Furthermore, suppose that a failed cell does not occur in the memory bank BANK1. Here, the number of failed cells which are repairable is limited to the number of redundancy cells of the redundancy memory area RED0.
When the number of failed cells of the memory bank BANK0 exceeds the number of failed cells which are repairable, the memory apparatus cannot be used any more. That is because, although the redundancy memory area RED1 formed in the memory bank BANK1 remains in a state where it is not used, data which are to be handled in the memory bank BANK0 cannot be routed to the redundancy memory area RED1.
Furthermore, in the known semiconductor memory apparatus 10, the main page buffers PB0 and PB1 and the redundancy page buffers RPB0 and RPB1 share I/O lines connected through the input/output control circuit 130. Therefore, a data input/output operation for the redundancy memory area is performed during a separate period from a period in which a data input/output operation for the main memory area is performed. Accordingly, the time required for the data input/output operation increases. As a result, the entire operation speed of the semiconductor memory apparatus is increased.
As the semiconductor memory apparatus 10 includes the redundancy memory area, a process of determining whether an address is a repair address or not is accompanied when data is programmed into or read from the memory area 110. In general, when the repair address is determined, CAM addresses stored in a register are compared to an external address one by one. However, when the above-described method is used to determine whether an address is a repair address or not, the time required for a program/read operation increases and thus data processing speed may decrease.